1. Field of the Invention:
The invention in general relates to integrated circuit memory arrays and more particularly with the row access topology of such memory arrays.
2. Statement of the Problem:
Integrated Circuit memories generally contain a two dimensional array of storage cells arranged in rows and columns. A common architecture is to connect all cells in a row to a common row line, often referred to as the "word line" and all cells in a column to a common column line often called the "bit line" or "digit line". In this architecture, the row line provides a signal which enables cells to receive or output a data signal and the column line provides the input or output line on which the signal is transferred. An individual cell is addressed via a row decoder that selects a row to be addressed and a column decoder which selects a column to be addressed, thereby selecting one particular cell at the corresponding row and column location. The cell is accessed by placing an enable signal on the row line in the row associated with the cell and reading or writing a signal on the column line associated with the cell.
Integrated circuit memories are also generally binary logic circuits in which information is stored and transferred as voltages representing complementary logic values that are alternately referred to as "true and false", "logic 1 and logic 0", or "logic high and logic low". Typically a voltage of 5 volts may represent the logic 1 state while a voltage of zero volts represents the logic 0 state. Because of the constraints of resistance, capacitance etc. the individual voltages input to or output on the column lines by individual cells are usually at some intermediate voltage. Thus subcircuits are associated with the column lines of integrated circuit memories to pull the high voltage values up to, or as close as possible to, the full logic 1 voltage, for example 5 volts, and to pull the low voltages down to as close to the logic 0 voltage, for example 0 volts, as possible. These subcircuits are commonly referred to as sense amplifiers. A common architecture utilizes a separate pull down subcircuit, referred to as an N-sense amplifier, to pull the low signals down to the logic 0 voltage, and a separate pull up subcircuit, referred to as a P-sense amplifier, to pull the high voltages up to the logic 1 voltage.
The invention to be disclosed herein is particularly applicable to an architecture used in dynamic random access memories (DRAM) and video random access memories (VRAM). In this architecture the individual memory cell comprises a transistor and a capacitor connected in series. One side of the capacitor is connected to a reference voltage, and the other side is connected to the column line through the transistor. The gate of the transistor is connected to the row line. Information is stored in the form of charge on the capacitor, which charge is input and output via the column line and gated by the row line acting on the transistor gate. There are tens or even hundreds of such cells connected to each column line. The column lines are organized into pairs with one N-sense amplifier and one P-sense amplifier associated with each pair. The N-sense amplifiers and P-sense amplifiers are connected across the pairs, with one column line going low and the other going high when one of the pairs of lines is addressed. The attachment of the transistor gates to row lines is staggered with the cells associated with adjacent pairs of column lines belonging to different rows so that the transistor which gates one of each associated pair will be off when a cell on the other of the pair is being addressed. That is, when a particular cell is addressed, the column line it is attached to will go high or low, depending on the cells content; the other column line or the pair will go to the opposite logic value. When the read or write cycle is over, the pairs are shorted together, which quickly brings them to a mid-voltage level, resetting them for the next cycle. In this way the pairing of the lines results in faster cycling of the circuit as a whole. Since the connection of the cells to the row lines are staggered, the transistor gates associated with the one of the line pair that is not being addressed are always off and the information in the cells is not affected by the column line of the non-addressed cells going high or low. This architecture is referred to as "divided bit line sensing". A common arrangement of the various parts of the circuit in the divided bit line sensing approach is to locate the column decoder and DRAM input and output terminals at one end of the column lines, the P-sense amplifiers at the other end of the column lines, and the N-sense amplifiers at the center of the column lines thereby dividing each the column lines into two halves, one half of the line extending between the N-sense amplifier and the column decoder and the other half extending between the N-sense amplifier and the P-sense amplifier. In VRAM a sequential-access memory (SAM) port is connected to the column lines on the opposite side of the P-sense amplifier from the column decoder.
As is well-known, integrated circuit memories are generally mass produced by fabricating hundreds of identical circuit patterns on a single semiconducting wafer, which wafer is subsequently sawed into hundreds of identical dies or chips. The advantages of building integrated circuits with smaller individual circuit elements so that more and more circuitry may be packed on a single chip are well-known: electronic equipment becomes less bulky, reliability is improved by reducing the number of solder or plug connections, assembly and packaging costs are minimized, and improved circuit performance, in particular higher clock speeds. However, the smaller the size of the individual cell, the smaller the size of the individual electrical components in the cell, and the smaller the electrical signals associated with them As more and more individual storage cells are placed onto a single chip, the length of the column lines connecting the individual cells to the amplifiers becomes longer and longer as compared to the individual cell size, and the capacitance associated with the lines becomes larger. This means that the signal transferred to the column line from an individual cell will become even smaller as the capacitance of the line absorbs the charge, and further that the time for developing a useful signal level on the line may increase. As is well known, speed is an important factor in such memories, since the faster the cells can be read, the faster is the computer of which the memory is a part, and the more operations the computer can do. Thus a number of enhancements have been made to DRAM and VRAM architecture to increase the signal level and amplifier response time. One such enhancement is described in U.S. Pat. No. 4,636,987. This patent describes an architecture in which a single column decoder is shared by four arrays, two arrays on either side of the column decoder. The row within the arrays are accessed symmetrically with respect to the column decoder: that is, a row in each of the arrays proximal to the column decoder are accessed in one access cycle, and a row in each of the arrays distal to the column decoder are accessed in a second access cycle. This access topology and related circuit design aspects provides a voltage doubling at the N-sense amplifiers and some convenience of design, but when further improvements described herein are added, it also results in uneven power use by the circuit. That is, as shall be seen in the detailed description below, when the circuit is accessing the arrays distal from the column decoder it generally draws more power than when it is accessing the arrays proximal to the column decoder. Such uneven power requirements means that the circuit power carrying capability must either be over-designed for the lower power cycles or under-designed for the higher power cycles, the first of which is wasteful and the second of which can result in decreased reliability and increased defects. Thus there is a need for a DRAM and VRAM architecture that allows the voltage doubling at the N-sense amplifiers and the improvements described below and at the same time has uniform power requirements in all access cycles.
For many applications of integrated circuit memories, such as for portable computers and other battery powered intelligent devices, the amount of power available is limited. Thus it is important that sense amplifiers not only are fast and small, but also consume a minimum of power. The largest component of the total power used in DRAM's is the charging and discharging of the column lines. Since all bits on the selected row line during an access must be refreshed, all the column lines must be charged or discharged. In the prior art, the entire column line had to be charged or discharged in every access. Therefore there is a need for an integrated circuit memory design in which this charging and discharging of digit lines is limited. In sum, it would be highly desirable to have an integrated circuit memory architecture that not only has uniform power requirements in all access cycles, but also decreases the maximum power consumed by the memory circuit. 3. Solution to the problem:
The present invention solves the above problems by providing a row access topology that is asymmetric with respect to the circuit input/output.
In DRAM, where the input/output port is associated with column decoder, one array distal from the column decoder is accessed in the same cycle as an array proximal from the column decoder. In VRAM, where the input/output port is associated with the SAM, one array distal from the SAM is accessed in the same cycle as an array proximal to the SAM.
The above-described asymmetrical access topology results in equal power requirements in all access cycles whether DRAM or VRAM is used.
Further, the timing signal which turns the isolation transistors on and off is altered from the prior art. The isolation transistors are controlled so that, in DRAM and VRAM, when the row being addressed is on the side of the N-sense amplifier nearer the input and outputs, the column line pair halves that are farther from the input and outputs are isolated from the N-sense amplifier during the both the N-sense and P-sense periods. That is, in DRAM, when the row being addressed is on the column decoder side of the N-sense amplifier, the isolation transistors on the SAM side of the N-sense amplifier remain off during both the N-sense and P-sense phases of the cycle, while in VRAM, when the row being addressed is on the SAM side of the N-sense amplifier, the isolation transistors on the column decoder side of the N-sense amplifier remain off during both the N-sense and P-sense periods. During the refresh cycle, the isolation transistors on the opposite side of the N-sense amplifier from the row being addressed remains off during both the N-sense and P-sense periods.
Further, the actuation of the individual P-sense amplifiers is controlled by a timing signal so that the P-sense amplifiers associated with the column line pair halves that are isolated from the inputs/outputs during the P-sense cycle do not fire, thus not charging the associated column line halves and saving power.